--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:16:52 12/02/2013
-- Design Name:   
-- Module Name:   H:/My Documents/Wery Punny Prochect/linesearcher/linesearcher_tb.vhd
-- Project Name:  linesearcher
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: marsrover
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY crossing_tb IS
END crossing_tb;
 
ARCHITECTURE behavior OF crossing_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT marsrover
    PORT(
         clk : IN  std_logic;
         sensor_l : IN  std_logic;
         sensor_m : IN  std_logic;
         sensor_r : IN  std_logic;
         reset : IN  std_logic;
         motor_l : OUT  std_logic;
         motor_r : OUT  std_logic;
         display_data : OUT  std_logic_vector(7 downto 0);
         display_enable : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal sensor_l : std_logic := '0';
   signal sensor_m : std_logic := '0';
   signal sensor_r : std_logic := '0';
   signal reset : std_logic := '0';

 	--Outputs
   signal motor_l : std_logic;
   signal motor_r : std_logic;
   signal display_data : std_logic_vector(7 downto 0);
   signal display_enable : std_logic_vector(3 downto 0);
	signal sensor : std_logic_vector(2 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: marsrover PORT MAP (
          clk => clk,
          sensor_l => sensor_l,
          sensor_m => sensor_m,
          sensor_r => sensor_r,
          reset => reset,
          motor_l => motor_l,
          motor_r => motor_r,
          display_data => display_data,
          display_enable => display_enable
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
	sensor_l <= sensor(0);
	sensor_m <= sensor(1);
	sensor_r <= sensor(2);

	reset <= '1' after 0 ns,
	         '0' after 100 ns;
   
	sensor <= "101" after 0 ns,
	          "000" after 200 ns,
	          "101" after 400 ns,
	          "010" after 500 ns,
	          "101" after 550 ns,
	          "000" after 700 ns;
			
			

END;


